Most surface-code roadmaps treat each logical qubit as its own square patch. A new paper from Google Quantum AI asks a modest but concrete question: can you take four ordinary surface-code patches, add a thin strip of ancilla qubits between them, and get a single block that stores two logical qubits at twice the patch distance, all on a planar nearest-neighbour chip? The authors say yes, back the claim with circuit-level simulations, and run the construction on a 105-qubit Willow processor.
This article was drafted with Claude and fact-checked against the cited primary sources.
Why this paper is worth reading
Concatenated codes and high-rate qLDPC codes promise fewer physical qubits per logical qubit, but they usually need connectivity that superconducting chips with a fixed square lattice do not have. Earlier hybrid schemes that put an outer code on top of surface-code patches (yoked surface codes, hierarchical memories) are aimed at large machines and, as the authors note, need too many qubits to show non-trivial distance scaling on current devices. This paper targets the opposite end: the smallest concatenation that still adds distance, built to fit hardware that exists today.
What the paper does
Mohamed A. Shalby, Leonid P. Pryadko and colleagues (including Craig Gidney) concatenate four distance-t rotated surface-code patches with the [[4,2,2]] code, the smallest CSS code with distance 2. The result is a [[4t2, 2, 2t]] code: two logical qubits at code distance d = 2t. Including all ancillas, the footprint is N = 2d2 + 4d − 3 physical qubits. For t = 3 that is 93 qubits for two logical qubits at distance 6.
The paper contributes three things:
a planar layout and syndrome-extraction schedule for the two outer-code checks,
a way to declare detectors so that the whole circuit can be decoded by ordinary minimum-weight perfect matching (MWPM), and
simulations plus a hardware memory experiment at d = 4 and d = 6.
The key idea: GHZ corridors
The [[4,2,2]] outer code has two stabilizer generators, XXXX and ZZZZ across the four patches. At the physical level each is a logical-operator product of weight 4t, spread over all four patches. The standard tools for measuring such an operator between surface-code patches are lattice surgery or long-range gates. Here the authors instead run narrow “corridors” of ancilla qubits in a cross shape between the patches. On each corridor they prepare a 4t-qubit GHZ state, check it, then couple it transversally to the relevant data qubits and read out the outer-stabilizer value in the Shor style.
The corridor overhead is 8t + 1 qubits, which grows only linearly with t. Corridor qubits next to a patch boundary also serve as that patch’s weight-two boundary ancillas: the boundary checks are switched off while those qubits are busy with the GHZ state and switched back on afterwards.
How it works
Preparation. The GHZ state is built by measurement: small GHZ clusters are fused by measuring intermediate qubits, giving a constant-depth circuit independent of t. The resulting Pauli corrections are not applied with feedforward; they are absorbed into the detector definitions.
Verification. One bad fault during preparation could leave a multi-qubit X error on the GHZ state that spreads into the data as a hook error. So each preparation is followed by rv rounds of pairwise ZZ parity checks along the corridor (XX checks on the other corridor). For patch distances up to 10 and rv ≥ 2, the authors find the circuit distance follows the empirical formula dcirc = min(2t, rv + 3). It was computed with Stim and cross-checked with dist_m4ri. So the full design distance needs rv = 2t − 3. The paper argues that fewer rounds are often better in practice, because the remaining short fault chains are confined to a few corridor sites. Each outer-generator measurement takes rv + 1 surface-code cycles.
Decoding. A fault in the corridor can trigger detectors in the corridor and in several patches at once (a “hyperedge”), which plain matching cannot handle. The authors declare the corridor and verifier detectors so that Stim breaks every such mechanism into graphlike pieces. The full syndrome, including the outer-code detectors, is then decoded in a single PyMatching pass, optionally with correlated reweighting.
What was demonstrated
Simulations (demonstrated numerically). Under the SI1000 superconducting-inspired noise model, the stitched code’s logical error rate scales as roughly pt, consistent with distance 2t. The authors compare it with two independent surface-code patches. At equal distance the stitched layout uses fewer qubits. To reach a target logical error rate, it overtakes two patches only above a crossover size: about N ≈ 157 at p = 10−4, ≈ 237 at p = 5×10−4 and ≈ 333 at p = 10−3. At p = (2–3)×10−3 its logical error rate at N ≈ 103 is still 10–14% higher than the two-patch baseline. Asymptotically the encoding density kd2/N tends to 1, twice the single-patch value of 1/2.
Hardware (demonstrated experimentally). On a 105-qubit Willow processor the team ran d = 4 (t = 2, rv = 1) and d = 6 (t = 3, rv = 2, circuit distance 5) memory experiments in both the ZZ and XX bases. They used 1 to 8 outer-code rounds (up to 52 surface-code cycles) and 200,000 shots per circuit. A four-state Markov model captures the correlated errors between the two logical qubits. With correlated matching, the per-cycle block error probability fell from 5.836% at d = 4 to 3.850% at d = 6, an improvement factor Λ4→6 = 1.516. With plain MWPM the numbers were 6.845% and 4.209% (Λ = 1.626). XX-basis runs had higher error rates than ZZ-basis runs, which the authors attribute to low-frequency phase noise.
Why it matters
The result is a working, matchable example of concatenation on a strictly planar nearest-neighbour lattice. No lattice surgery, long-range couplers or workspace patches are needed. The authors also point out a geometric benefit: both logical qubits sit in one nearly square region rather than a rectangle of two patches. That could matter for tiling, packaging and modular designs, independent of qubit count. They also suggest the corridor gadget could carry other small outer codes whose checks can be routed through planar corridors.
Technical perspective (interpretation)
My reading is that the paper’s most reusable contribution is the decoder-friendly detector design rather than the specific [[4,2,2]] block. Weight-4t checks measured through a GHZ state normally produce exactly the hyperedges that push people towards slower decoders such as BP+OSD or search-based decoding. Showing that careful detector declarations keep everything matchable is a practical result for anyone designing gadgets that act across patches.
The experiment should be read as a feasibility and scaling check, not a memory record. Per-cycle block error probabilities of a few percent are far from what single-patch surface-code memories on Willow-class hardware have shown. The paper itself says the device’s physical error rates lie above the simulated crossover where stitching starts to save qubits. As far as I can see, the main text reports no same-device surface-code baseline. So the hardware data show that error per cycle drops with distance, not that the stitched code beats ordinary patches today.
Limitations and open questions
Slow outer-code parity. The outer-code detectors fire often (close to 1/2 at d = 6 on hardware) because the checks have large physical weight. A memory can tolerate this; a timed parity measurement cannot. In a stability simulation at p = 10−3, the t = 3 stitched code needed about 80 cycles to determine GX with error probability 10−3, against about 5 cycles for a surface code of the same distance. The authors conclude that logical operations should go through patch boundaries or code automorphisms, not the corridors.
Footprint advantage is conditional. It depends on the physical error rate and the target logical error rate, and needs t large enough to amortise the corridor noise.
Circuit distance below code distance in the experiment. The d = 6 hardware circuit used rv = 2, giving circuit distance 5.
Hardware demands. Some qubits that would normally be data qubits become corridor ancillas, so they must be measured and reset every outer round. The hardware is not optimised for that.
Open directions named by the authors: optimising corridor readout, reset and leakage removal; other planar-routable outer codes; logical gates on and between stitched blocks.
Paper information
Title: Stitched surface codes: planar concatenation through GHZ corridors
Authors: Mohamed A. Shalby, Alexandre Bourassa, Amir Karamlou, Leigh Martin, Alexis Morvan, Nicholas Noll, Craig Gidney, Leonid P. Pryadko (Google Quantum AI; M. A. Shalby also University of California, Riverside)
arXiv: 2610.21357v1 [quant-ph], submitted 15 October 2026
Length: 18 pages, 16 figures, 4 tables
Code and data: the paper points to github.com/QEC-pages/Stitched-Surface-Code. When this article was written (16 October 2026) that URL returned “page not found”, so the repository may not be public yet.
Primary sources
arXiv abstract page: arxiv.org/abs/2610.21357
Full text (HTML): arxiv.org/html/2610.21357v1